1. Field of the Invention
This invention relates to integrated circuit structures formed on a semiconductor wafer. More particularly, this invention relates to an integrated circuit structure having an electrode with a roughened surface formed thereon, and a process for forming same.
2. Description of the Related Art
In the formation of integrated circuit structures on semiconductor wafers, it is sometimes desirable to provide, on a conductive element such as an electrode, a roughened surface. Such a roughened surface, for example, is useful on the surface of a floating gate facing the control gate in an erasable programmed read only memory (EPROM) device. Such a roughened surface, or asperities, formed on the floating gate of an EPROM device cause a more desirable controlled breakdown of the oxide between the floating gate and the control gate, known as Fowler-Norheim tunneling, rather than an avalanche breakdown through the oxide during discharge of the floating gate electrode.
However, such formation of a roughened surface of controlled texture, for example, on a metal or silicon surface, is not always easily accomplished on a reliably reproducible basis.
It would, therefore, be desirable to provide an integrated circuit structure having a conductive member, such as a floating gate in an EPROM, with a surface of controlled roughness thereon, and a process for forming same.